1. Field of the Invention
The present invention relates to a parallel-to-serial conversion circuit, and more specifically to a circuit for converting a PCM code to a 2'complement code in accordance with a so called "A-law regulation".
2. Description of Related Art
A conventional parallel-to-serial data conversion circuit for converting an 8-bit parallel data of PCM code to a 14-bit serial data of 2'complement in accordance with the "A-law regulation" is composed of shift registers (See for example, Document: "Digital Electric Circuit" (Japanese language)/SHOKODO (Inc,) in Japan, pp 132-135) in accordance with "13-segment A-law regulation decoding table (See for example, Document: "Transmission Engineering" (Japanese language)/Ohm Company in Japan, pp 132-141)).
One example of a specific construction of the prior art conversion circuit is shown in the block diagram of FIG. 1. As shown in FIG. 1, The parallel-to-serial data converter is composed of an 8-bit input/14-bit output decoder DCB10 which receives an 8-bit parallel PCM input dam I(7), I(6), . . . , I(1), I(0), and a shift register SRB10 which receives a clock signal (CLOCK), a store signal (STORE) and a load signal (LOAD) and a 14-bit output data d(13), d(12),. . . , d(1), d(0) of the DCB10 and which outputs a 14-bit serial data of 2'complement code to an output terminal OUT.
Now, operation of this circuit. Will be explained with reference to FIGS. 2 to 4, a combination of which illustrates, as a whole, a detailed circuit diagram of the circuit shown in FIG. 1. Wiring conductors shown in FIG. 2 and designated with Reference Numerals 1 to 30 are connected to wiring conductors shown in FIG. 3 and designated with the same Reference Numerals, and wiring conductors shown in FIG. 3 and designated with Reference Numerals 31 to 39 are connected to wiring conductors shown in FIG. 4 and designated with the same Reference Numerals.
As shown in FIGS. 2 to 4, the conversion circuit includes selectors SE50 to SE54 and SE58 to SE62 which receive the 8-bit parallel PCM input data I(7), I(6), . . . , I(1), I(0), an inverter I30, an AND gate A30, an OR gate 030, selectors SE30 to SE32 and SE39 to SE42 controlled by the store signal, D-type latches D43 to D40 and D32 to D30, which are connected as shown in FIGS. 2 to 4. Further, the conversion circuit includes the output terminal OUT connected to a Q output of the D-type latch D30, for outputting the 14-bit serial data of 2'complement code (LSB first).
FIGS. 5 and 6 show timing; charts illustrating an operation of circuits shown in FIGS. 2 to 4. More specifically, FIG. 5 shows waveforms of the clock signal CLOCK, the: store signal STORE, the load signal LOAD, the 8-bit PCM parallel data input I(7) to I(0), and the output data d(13), d(12), d(11) of the decoder DCB10 by using the CLOCK signal as a reference. The successive output data d(10), d(9), . . . , d(0) of the DCB10 and the signal on the output terminal OUT (serial data output of 2'complement code) are shown in FIG. 6. One timing chart is shown by a combination of FIG. 5 and FIG. 6. Now, only the data d(11) is shown in both of FIG. 5 and FIG. 6. In FIG. 5 and FIG. 6, "1" and "0" are indicative of a logical value.
A table for convening the 8-bit PCM code into the 2'complement code is shown in FIGS. 7 to 14. In FIG. 7 to FIG. 14, "A-law regulation", PCM code, 2'complement (14 bits) are shown in order.
The data of an 8-bit PCM code is converted to a parallel data of 2'complement code, excepting for the MSB bit and the LSB bits, in accordance with the "A-law regulation" shown in FIGS. 7 to 14, by the parallel data bits I(4), I(5), I(6) and I(7) of the 8-bit PCM code, and also by the selectors SE50 to SE62 selecting a "L" (low) level (GND), a "H" (high) level (VDD) and the parallel data bits I(3), I(2), I(1), I(0) of the 8-bit PCM code. The LSB bit is ceaselessly at the "L" level, and the MSB bit is an output of the inverter 30 which inverts the parallel data bit I(7) of the 8-bit PCM code. The outputs d(0) to d(12) of the selectors SE50 to SE62 are inputted into the A terminal of the selectors SE30 to SE42. The terminal B of the selectors SE50 to SE62 receives the outputs of the latches D30 to D43, which in turn receive as a clock signal an AND signal of a predetermined clock signal CLOCK and a predetermined load signal LOAD. A predetermined store signal STORE is inputted into a select input S of the selectors SE30 to SE42.
If the predetermined STORE signal is applied, the selectors SE30 to SE42 select their A input, and the A inputs are supplied into the latches D30 to D42, respectively. The output D(13) of the inverter 130 (that is the inverted signal of the input 8-bit PCM code parallel data bit I(7)) is latched into the latch D43. The selectors SE30 to SE42 select their B input when the predetermined LOAD signal is applied, and the 14-bit serial output data of 2'complement code is outputted from the latch D30 in an "LSB-First" fashion.
As will be apparent from the above description, the conventional parallel-to-serial data conversion circuit for converting an 8-bit PCM code parallel data to a 14-bit serial data of 2'complement code, requires the 8-bit input/14-bit output decoder to have a complicated circuit construction. Therefore, the circuit scale is large. In addition, since the PCM code is converted to the 2'complement code while maintaining the parallel data, the latches of the number corresponding to the bit number of the outputs data of 2'complement code (14 bits) are required for converting the parallel data into the serial data. Accordingly, the circuit scale becomes even larger.